Test Time Optimization in Scan Circuits

As circuit sizes increase with scale down in technology, the time required to test the circuits also increases. Expensive automatic test equipment (ATE) is used to test these circuits and the cost of testing becomes a significant fraction of the total cost of the chip. Testing cost of a chip is directly related to the time its testing takes. However, test time cannot be reduced by simply applying the tests at a faster speed because if the test clock frequency is increased, the power consumed during test increases. If this power were to exceed the power consumption the chip can withstand, the circuit might perform slower or might malfunction [52]. This research aims at reducing the time required for test without increasing the power dissipated during test. Full scan design is a popular design for testability (DFT) method [11] in which the flip-flops of the circuit are chained together to function as a shift register during test. Test vectors are scanned in and the responses are scanned out bit by bit. The power consumption during test can exceed the power consumption in the functional mode of operation [12, 53] due to high activity required to achieve high test coverage for the circuit under test. Therefore, the scan-in and scan-out of vectors are normally carried out at frequencies much lower than functional frequencies. However, all vectors do not create the same amount of activity in the circuit. The vectors that cause low activity in the circuit can be scanned in at higher frequencies without exceeding the power limit. A scheme to reduce test application time by dynamically increasing the scan clock frequency is proposed. The test power is held below the allowed power limit by controlling the activity per unit time. The per cycle scan activity is monitored dynamically to speed up the scan clock for low activity cycles without exceeding the specified peak power budget. The